1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor package called a COF (Chip On Film) structure wherein a substrate and a semiconductor element are connected by a flip flop method.
2. Description of the Related Art
FIG. 6 is a bottom view of a semiconductor element or chip having a COF structure according to a conventional example, FIGS. 7(a) and 7(b) are respectively a top plan view of a substrate employed in the COF structure according to the conventional example and a cross-sectional view taken along line A–A′ of FIG. 7(a), FIG. 8 is a cross-sectional view taken along line A–A′ of FIG. 7(a), showing a state in which the substrate and the semiconductor element employed in the conventional example have been connected, and FIG. 9 is a cross-sectional view taken along line A–A′ of FIG. 7(a), showing a state in which the COF structure according to the conventional example has been sealed, respectively. The conventional COF structure will be explained below.
As shown in FIG. 6, bump electrodes 2 are formed on an undersurface of a semiconductor element 1. The bump electrodes 2 are normally formed at a peripheral portion lying within the semiconductor element 1.
As shown in FIGS. 7(a) and 7(b), a plurality of wirings 4 are formed over a substrate 3, and the substrate 3 and the wirings 4 are covered with an insulating film 5. A polyimide film having flexibility, which has a thickness of 25 μm or 40 μm, is used for the substrate 3. However, the thickness of the substrate 3 described herein can be suitably set. A barrier metal 6 (nickel [Ni] and chromium [Cr] or nickel [Ni] and copper [Cu]) is sputtered on the surface of the substrate 3. Copper is then precipitated on the barrier metal 6 by a plating method to form a copper foil. The copper foil is subjected to photolitho and etching, whereby a plurality of the wirings 4 are formed. At least the wirings 4 at bump electrode connecting positions 7 are given tin plating. The wirings 4 extend from the periphery of the substrate 3 to a semiconductor element mounting area 8. The wirings 4 at the bump electrode connecting positions 7 are positioned so as to correspond to the bump electrodes 2 of the semiconductor element 1 within the semiconductor element mounting area 8. The insulating film 5 is formed so as to expose at least the semiconductor element mounting area 8. This is done to keep wide a space used as a hole for injection of an encapsulating material 9, which is defined between the substrate 3 and the end of the semiconductor element 1 upon sealing a space defined between the substrate 3 and the semiconductor element 1 by means of the encapsulating material 9 and facilitate the injection of the encapsulating material 9, as shown in FIG. 9.
As shown in FIG. 8, the wirings 4 at the bump electrode connecting positions 7 on the substrate 3, and the bump electrodes 2 formed on the semiconductor element 1 are respectively brought into alignment by a bonding device and electrically connected to one another. A thermocompression bonding method or the like is normally used as a method for connecting them. The thermocompression bonding method is a method of applying heat and pressure to the wirings 4 at the bump electrode connecting positions 7 and the bump electrodes 2 and melting tin plated onto the wirings 4 at the bump electrode connecting positions 7 to thereby connect the wirings 4 to the bump electrodes 2.
As shown in FIG. 9, the space defined between the substrate 3 and the semiconductor element 1 is sealed with the encapsulating material 9 injected through the space defined between the substrate 3 and the end of the semiconductor element 1. A resin is normally used as the encapsulating material 9.
FIG. 10 is a cross-sectional view taken along line A–A′, showing a COF structure according to a conventional example where an edge short has occurred. In the COF structure according to the conventional example as shown in FIG. 10, there may be a case in which when wirings 4 and bump electrodes 2 are thermocompression-bonded, a substrate 3 is deformed due to heat and pressure as designated at numeral 10. In this case, there is a possibility that an edge-short problem will arise in that since the wirings 4 located on the downside of a semiconductor element 1 and its periphery are not covered with an insulating film 5, the wirings 4 are brought into contact with the semiconductor element 1 at a spot designated at numeral 10 so that the wirings 4 and the semiconductor element 1 are short-circuited.